Roving Concurrent Error Detection for Logic Circuits

The continuous increase in the complexity of current designs generates logic circuits that are less immune to soft errors. As the soft error rate increases, Concurrent Error Detection (CED) techniques are becoming ever more essential. A plethora of research efforts have been expended in developing CED techniques that provide high levels of reliability [1, 2, 3]. Yet, the high overhead associated with these CED methods led to little attention in the industry. In a recent trend, low-cost CED methods [4, 5, 6] have been proposed that trade fault coverage for area overhead. Low-cost CED in logic circuits is more appealing to the industry as it increases the reliability of a circuit at an acceptable area overheard. In this paper, we present a new method for the synthesis of low-cost CED circuitry for logic circuits based on the notion of test roving. As illustrated in figure 1.a, multiple substructures that appear twice in a logic circuit are extracted and added to the CED circuitry in figure 1.b. In addition, we duplicate all the gates that are not part of a substructure in the roving CED circuitry to provide complete test of all potential failure points. As the circuit operates, every substructure in the CED circuitry roves -using input and output multiplexorsbetween the two instances that it matches. An output comparator is utilized to detects any faults in the substructure being tested.